Field
The present disclosure relates generally to integrated circuits, and more particularly, to pseudo dual port (PDP) memories.
Background
A dual port memory handles both a read and a write operation within a single clock cycle. A dual port memory typically includes two ports operating with an array of memory cells, which may be simultaneously accessed from both ports.
In order to reduce the area occupied by memory, a pseudo dual port (PDP) memory may be used to replace a dual port memory. The core of the PDP memory is a single-core memory which provides a single memory access, and not two simultaneous memory accesses as with the dual port memory. The PDP memory is, however, configured to emulate the dual port memory by sequentially performing two memory accesses in a memory cycle. For example, in a particular memory cycle, the PDP memory may perform a read operation and, then, perform a write operation.